The present invention relates to a semiconductor apparatus, a degradation value determination system, and a processing system.
International Patent Publication No. WO2011/27553 (hereinafter referred to as “Patent Literature 1”) discloses an aged-degradation diagnosis apparatus using ring oscillators. The apparatus disclosed in Patent Literature 1 includes a test ring oscillator, a reference ring oscillator, load means, comparison means, and control means. The test ring oscillator and the reference ring oscillator include logic gates having the same configuration as each other. The control means makes the test ring oscillator and the reference ring oscillator simultaneously oscillate by using a common control signal.
The load means supplies a load signal to the test ring oscillator and the reference ring oscillator. Specifically, the load means advances the degradation of the logic gates included in the test ring oscillator by applying a load signal to the test ring oscillator for a predetermined time period. In this state, the power supply terminal of the reference ring oscillator is connected to a GND and hence the reference ring oscillator is brought into a state under no stress (paragraph [0027]). As a result, the degradation of the logic gates included in the reference ring oscillator hardly advances.
After that, the control means simultaneously supplies a control signal to the reference ring oscillator and the test ring oscillator. Then, the comparison means compares the amount of the shift of pulses of the reference ring oscillator with that of the test ring oscillator. Specifically, a counter circuit counts pulses of the reference ring oscillator and those of the test ring oscillator. Then, the comparison means compares these count numbers with each other and thereby calculates the amounts of the shifts of pulses of the reference ring oscillator and the test ring oscillator.
Japanese Unexamined Patent Application Publication No. 2013-88394 (hereinafter referred to as “Patent Literature 2”) discloses a semiconductor apparatus including a ring oscillator including multi-stage gate components, and a delay monitor that measures a delay of the ring oscillator. In the semiconductor apparatus disclosed in Patent Literature 2, a CPU (Central Processing Unit) controls a power supply voltage and an operating frequency according to the delay time measured by the delay monitor. Further, when the delay time exceeds a reference value, the CPU determines that an LSI (Large Scale Integration) has deteriorated over time and hence gives a warning.
Further, Patent Literature 2 discloses a configuration in which a pair of two delay monitors is used (FIG. 19). A ring oscillator of the first delay monitor continues oscillating except for predetermined cycles before and after a measurement period. Meanwhile, a ring oscillator of the second delay monitor oscillates only in the measurement period. Therefore, since the oscillating time of the ring oscillator of the first delay monitor is longer than the oscillating time of the ring oscillator of the second delay monitor, the ring oscillator of the first delay monitor deteriorates earlier than the ring oscillator of the second delay monitor. Further, when a difference between the delay times measured in the two delay monitors exceeds a reference value, the CPU determines that the LSI has deteriorated over time.